STUPIDSID
1 (a)
Define Instruction Set Architecture (ISA). Explain seven dimensions of an ISA.
8 M
1 (b)
Find the number of dies per 500 mm water for a die that is 2.0 cm on a side.
4 M
1 (c)
Explain main measures of dependability.
4 M
1 (d)
Derive CPU time in term of instruction cycle and cycles per instruction.
4 M
2 (a)
Explain basic of a RISC instruction set.
5 M
2 (b)
Show with diagram, how data hazard stalls are minimized by forwarding method.
7 M
2 (c)
List the types of exceptions. Explain requirements on exceptions.
8 M
3 (a)
Define ILP. Explain data dependencies and hazard in detail.
8 M
3 (b)
With finite state processor, explain 2-bit prediction scheme.
5 M
3 (c)
Explain hardware based speculation with steps involved in instruction execution.
7 M
4 (a)
What are the three major flavours of multiple issue processor? Summarize the basic approaches to multiple issue and their distinguishing characteristics.
8 M
4 (b)
Explain branch target buffer with neat diagrams.
6 M
4 (c)
What are the issues involved in implementation of speculation? Explain register renaming approach.
6 M
5 (a)
Explain taxonomy of parallel architecture according to Flynn.
6 M
5 (b)
To achieve a speed-up of 80 with 100 processors, what fraction of the original computation can be sequential?
6 M
5 (c)
Explain the basic of directory based cache coherence protocol.
8 M
6 (a)
Assume a computer where the clocks per instruction is 1.0 when, all memory accesses hit in the cache. Only data accesses are loads and stores, and these total 50% of the instructions. If the miss penalty is 25 clock cycles and the miss rate is 2% how much faster would the computer be if all instruction were cache hits?
6 M
6 (b)
Explain following cache optimizations:
i) Higher associativity to reduce miss rate
ii) Read misses over writes to reduce miss penalty.
i) Higher associativity to reduce miss rate
ii) Read misses over writes to reduce miss penalty.
8 M
6 (c)
Explain techniques for fast address translation.
6 M
7 (a)
Explain 'compiler optimizations to reduce miss rate' in advanced cache optimization.
8 M
7 (b)
Explain DRAM memory technology with its basic organization.
8 M
7 (c)
Write a note on protection via virtual machines.
8 M
8 (a)
Explain loop level dependencies by considering following code:
for (i=1; i<=100; i=i+1) {
A[i]=A[i]+B[i];
B[i]=C[i]+D[i]; }
for (i=1; i<=100; i=i+1) {
A[i]=A[i]+B[i];
B[i]=C[i]+D[i]; }
6 M
8 (b)
Explain software pipelining with symbolic loop unrolling.
9 M
8 (c)
List and explain five execution unit slots in the IA-64 architecture with example instructions.
5 M
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