Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary


1 (a) Draw and explain y chart in detail.
7 M
1 (b) Explain design procedure steps for fabrications of p-MOS transistor.
7 M

2 (a) Explain Channel Length Modulation.
7 M
Answer any two question from Q2 (b) or Q2 (c)
2 (b) Draw and explain the structure of MOSFET transistor. Derive the expression for Threshold of MOSFET transistor.
7 M
2 (c) What kind of approximation is used to establish MOSFET voltage current relationship? With the help of that derive the expression which gives the relation between input voltage (Vgs) and current (Id).
7 M

Answer any two question from Q3 (a), (b) or Q3 (c), (d)
3 (a) Draw the CMOS inverter circuit and VTC for different operating regions of the nMOS and PMOS transistor. Derive VOH,VOL,VIH and VIL.
7 M
3 (b) Explain Device Isolation Technique and Locos.
7 M
3 (c) Give the delay time definitions and calculation of delay times.
7 M
3 (d) Write a short note on MOSFET Capacitance.
7 M

Answer any two question from Q4 (a), (b) or Q4 (c), (d)
4 (a) Concept of regularity, modularity and locality.
7 M
4 (b) Write a short note on FPGA.
7 M
4 (c) Explain Gradual Channel Approximation of MOSFET.
7 M
4 (d) Explain the MOS system under external bias.
7 M

Answer any two question from Q5 (a), (b) or Q5 (c), (d)
5 (a) Explain two input depletion load NOR gate and derive the necessary equations for the same.
7 M
5 (b) Explain the basic principle of pass transistor circuit. Explain logic "1" transfer and logic "0" transfer.
7 M
5 (c) Explain Depletion Load nMOS inverter.
7 M
5 (d) Write a short note on Built In Self Test (BIST).
7 M



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