STUPIDSID
1 (a)
Discuss VLSI design flow in brief. ( Y - chart).
7 M
1 (b)
Explain design procedure steps for fabrications of n-MOS transistor.
7 M
2 (a)
Explain Channel Length Modulation.
7 M
Answer any two question from Q2 (b) or Q2 (c)
2 (b)
Explain energy band diagram of MOS structure at surface inversion and derive the equation of threshold voltage.
7 M
2 (c)
Explain major types of capacitances and show its variation under different operating regions and physical parameters.
7 M
Answer any two question from Q3 (a), (b) or Q3 (c), (d)
3 (a)
Draw the CMOS Inverter circuit and VTC for different operation regions of the nMOS and pMOS transistor. Derive critical voltage points VOH, VOL, VIL and VIH.
7 M
3 (b)
Discuss basic steps of the LOCOS Process.
7 M
3 (c)
Derive the expression for drain current as a function of VGS, VDS and VSB for all three region of operation of MOSFET using Gradual Channel Approximation.
7 M
3 (d)
Explain two different down scaling techniques for MOSFET. Which technique is preferable?
7 M
Answer any two question from Q4 (a), (b) or Q4 (c), (d)
4 (a)
Explain the functioning of depletion load nMOS inverter and derive critical voltage points VOH, VOL, VIL and VIH.
7 M
4 (b)
Concept of regularity, modularity and locality.
7 M
4 (c)
Explain delay time definitions for MOS Inverters Switching Characteristics and derive the Expression for λPHL & λPLH.
7 M
4 (d)
Writes a short note on Design Quality.
7 M
Answer any two question from Q5 (a), (b) or Q5 (c), (d)
5 (a)
Discuss Complementary pass transistor logic. Realize the XOR gate using CPL.
7 M
5 (b)
Explain the criteria to measure the design quality to improve the chip design and explain any two in brief.
7 M
5 (c)
List the important concern for the IC packaging technology. Also Explain different packaging technologies.
7 M
5 (d)
Write a short note on Built In Self Test (BIST).
7 M
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